The present invention relates to a controlled soft programming method for non-volatile memory cells, in particular of the flash EEPROM and EPROM type.
As is known, in general, the erasing operation of flash cells takes place by means of Fowler-Nordheim tunneling, and is carried out in parallel on all the flash cells belonging to a single memory sector.
In this respect, FIG. 1 shows a sector 2 of a flash-type memory 1, formed by a plurality of cells 3 which are disposed on lines and columns, and are connected to respective word lines 4 and bit lines 5.
In detail, the cells 3 which are disposed on a single line have gate terminals which are connected to a single word line 4, in turn connected to a line decoder 8; the cells 3 which are disposed on a single column have drain terminals which are connected to a single bit line 5, in turn connected to a column decoder 9. All the source terminals of the cells 3 are connected to one another, and are available outside the sector 2 via a common source line 6, and all the bulk terminals of the cells 3 are connected to one another, and are available outside the sector 2 via a common bulk line 7.
The line decoder 8 and the column decoder 9 address in a known manner the word lines 4 and the bit lines 5 which are connected to them.
With reference to FIG. 2 and to the wiring diagram shown in FIG. 1, the erasing operation of the sector 2 by Fowler-Nordheim tunneling takes place by supplying one or more erasing pulses to the cells 3. More specifically, for a pre-determined time, which is equivalent to 10-40 ms, a voltage VB which increases in a non-linear manner is supplied to the common bulk line 7, starting from a minimum potential which is equivalent to 0V, up to a maximum potential which is equivalent to 8V (FIG. 2).
Simultaneously, all the word lines 4 are biased to a negative voltage (xe2x88x922V) by means of the line decoder 8, whereas all the bit lines 5 and the common source line 6 are left floating.
By this means, below the floating gate regions 15 of the cells 3, there is created a transverse electrical field, having an intensity such as to permit extraction of the electrons which have remained trapped in this floating gate region 15, after a preceding programming operation. The threshold voltage of the cells 3 is consequently lowered to a first pre-determined threshold value.
One of the problems which is encountered most frequently in erasing of memory cells is that after the erasing pulses have been applied, some memory cells are erased excessively, until a threshold voltage which is too low, or even negative, is obtained. These cells are thus in a conductive state, although their respective word lines are biased to ground (depleted cells).
It is known that in a non-volatile memory having a NOR configuration, the presence of depleted cells can distort the subsequent reading operation of the memory itself. In memories of this type, it is therefore necessary to have the erasing operation followed by a soft programming operation of the depleted cells.
This soft programming operation consists of biasing a pre-selected group, or, as an alternative, all the cells belonging to a memory sector previously erased, such as to produce in the cells an increase in the threshold voltage, to above a second predetermined threshold value. In greater detail, within the floating gate region of the cells belonging to the pre-selected group or to the memory sector erased, there is generated a flow of hot electrons, with an intensity and duration such as to increase the threshold voltage of the cells such that depleted cells are no longer present.
For this purpose, according to patent U.S. Pat. No. 5,546,340, one or more soft programming pulses are supplied to a pre-selected group of cells (hereinafter defined as pre-selected cells), belonging to the memory sector previously erased, or to all the cells in the sector. More specifically, for a pre-determined time of a few microseconds, the word lines which are connected to the gate terminals of the pre-selected cells are biased to a constant positive potential. This potential is such as to guarantee that none of the preselected cells reaches a threshold voltage which is higher than a pre-determined maximum threshold value.
Simultaneously, a constant positive potential is applied to the bit lines which are connected to the drain terminals of the pre-selected cells.
On the other hand, the common source line and the common bulk line are connected respectively to ground and to a pre-determined constant negative potential.
However, this known solution has the disadvantage that during the step of soft programming of the memory cells, the drain current of these cells has somewhat high values. In particular, when the soft programming is started, the drain current has a very high peak, owing to the fact that the overdrive voltage of the cells to be programmed (which is defined as the difference between the gate-source voltage and the threshold voltage) is somewhat high, owing to the initial low value of the threshold voltage.
In order to eliminate this disadvantage, according to patent EP-A-0 908 895, there is applied to the word lines which are connected to the pre-selected cells a ramp voltage rising linearly, from a minimum potential to a maximum potential.
Although it is advantageous in various respects, this known solution has the disadvantage that, for initial values of the ramp voltage, the transverse electrical field which is created below the floating gate region of the pre-selected cells is limited. Consequently, there is a low level of efficiency in the injection of hot electrons into the floating gate region, and therefore a low level of efficiency of soft programming.
The technical problem on which the present invention is based consists of eliminating the limitations and disadvantages previously described.
According to one aspect of the present invention, there is provided a method for controlled soft programming of non-volatile memory cells, where each cell has a control gate terminal and a bulk terminal, the bulk terminal of each cell connected to the bulk terminal of each other cell and to a common bulk line. According to one aspect of the invention, the method includes applying a voltage with a linearly rising negative ramp to the bulk terminals of the cells, and simultaneously supplying one or more soft programming pulses to the control gate terminal of the cells during a predetermined time interval.
According to another aspect of the invention, the soft programming of the cells is alternatively applied to a predetermined subset of the cells.
According to still another aspect of the invention, the cells to be soft programmed are soft programmed as a function of the rising bulk voltage level. Preferably, soft programming the subset of cells as a function of the rising bulk voltage level includes applying an initial negative bulk voltage to the cells to be soft programmed and subsequently gradually increasing the bulk voltage to a maximum value, whereby the cells in the subset of cells are soft programmed as a function of the level of depletion in the cells.
According to yet other aspects of the invention, the invention includes a non-volatile memory device having a multiple memory cells, each cell having a bulk terminal connected to the bulk terminal of each other cell and to a common bulk line. The non-volatile memory device of the invention also includes a bulk biasing unit connected to the common bulk line, the bulk biasing unit including a voltage generator with a rising negative ramp. The rising negative ramp further defining either a square wave or a ramp rising substantially linearly from a negative value.